>Dpu-Mir-96-P2_pre
CUUGGCACUGGAAGAAUUCACAGAGUGCAUUACGACAGGUCGUGGGUUCCCUGGUGCCAGAGA
>Dpu-Mir-96-P2_pri
AUAUGUAGGAAAUUAAAUAUUCCGGUGAUCCUUGGCACUGGAAGAAUUCACAGAGUGCAUUACGACAGGUCGUGGGUUCCCUGGUGCCAGAGAUUGCUCCCGGAAAUCAAUAUCAUCACAAUU
>Dpu-Mir-96-P2_loop
GUGCAUUACGACAGGUC
>Dpu-Mir-96-P2_5p
CUUGGCACUGGAAGAAUUCACAGA
>Dpu-Mir-96-P2_3p*
GUGGGUUCCCUGGUGCCAGAGA
>Dpu-Mir-96-P3_pre
AAUGGCACUGGAAGAAUUCACGGGUCGCAAUUAAAUUUGACAGAUUUGAAUUUCUGGAAAAUGACACACUCGUGGAUCUUCAGUGCUGUACC
>Dpu-Mir-96-P3_pri
AUAUGUCGGUUGUUGUUGGCCGAUUCCCGCAAUGGCACUGGAAGAAUUCACGGGUCGCAAUUAAAUUUGACAGAUUUGAAUUUCUGGAAAAUGACACACUCGUGGAUCUUCAGUGCUGUACCGGGCGUCGGUUAUUCCAUCUUCUACUUAUC
>Dpu-Mir-96-P3_loop
UCGCAAUUAAAUUUGACAGAUUUGAAUUUCUGGAAAAUGACACACU
>Dpu-Mir-96-P3_5p
AAUGGCACUGGAAGAAUUCACGGG
>Dpu-Mir-96-P3_3p*
CGUGGAUCUUCAGUGCUGUACC